UVVM Presentation++ in Bergen 28. September 2015
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UVVM Presentation++ in Bergen 28. September 2015

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The following presentations will be given in Bergen Monday Sept. 28, 2015.
(at Bergen University College).

In the morning – a Guest lecture – primarily for students at University of Bergen and Bergen University College, but also open for FPGA designers from the industry.

10:15 – 12:00 Making a simple testbench – step-by-step
12:15 – 13:00 Developing an FPGA module with a strong focus on efficiency, quality and modifiability
(See more details)

14:00 – 14:30 The critically missing VHDL testbench feature – Finally a structured approach
14:30 – 16:00 Universal VHDL Verification Methodology (UVVM) – Tutorial
(See more details)