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The critically missing VHDL testbench feature – Finally a structured approach (@FPGAworld, Stockholm, 8 Sept 2015)

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Verification is 51% of total FPGA development time (cf ‘Functional Verification Study’ from Wilson Research Group). Even more for control or protocol oriented design.
Ignore this and you will iterate forever in the lab and suffer from bad product quality. The root cause is corner cases triggered by certain input and FSM combinations. Hitting a given corner case in normal simulation is very unlikely, – but in the final product it will hit you hard. A structured VHDL approach to verifying such corner cases has not been commonly available. UVVM (Universal VHDL Verif. Meth.) changes this picture completely..