Xilinx Zynq 7000
The Zynq®-7000 All Programmable SoC (AP SoC) family integrates the software programmability of an ARM®-based processor with the hardware programmability of an FPGA, enabling key analytics and hardware acceleration while integrating CPU, DSP, ASSP, and mixed signal functionality on a single device.
Microblaze or LEON3 soft-Cores
Dual ARM Cortex-A9
intel Cyclone V
Cyclone® V SoCs provide low system cost and power. The SoC FPGA high-performance levels are ideal for differentiating high-volume applications, such as industrial motor control drives, protocol bridging, video converter and capture cards, and handheld devices. SoC FPGAs come in a wide range of programmable logic densities with many system-level functions hardened in silicon — a dual-core ARM* Cortex*-A9 Hard Processor System (HPS), embedded peripherals, multiport memory controllers, serial transceivers, and PCI Express* (PCIe*) ports.
Nios II or LEON3 soft-Core
Dual ARM Cortex-A9
Nios® II processor, the world's most versatile processor, according to Gartner Research, is the most widely used soft processor in the FPGA industry. The Nios II processor delivers unprecedented flexibility for your cost-sensitive, real-time, safety-critical (DO-254), ASIC-optimized, and applications processing needs. The Nios II processor supports all Intel® FPGA and SoC families.
MicroBlaze™ is a key element of Xilinx’s Embedded Product Portfolio. As a full-featured, FPGA optimized 32-bit Reduced Instruction Set Computer (RISC) soft processor, Microblaze meet requirements for diverse applications such as industrial, medical, automotive, consumer, and communication infrastructure markets among others. MicroBlaze is a highly configurable and easy to use processor and can be used across FPGAs and All Programmable (AP) SoC families. It is included free with Vivado® Design and System Edition and Vivado Webpack Edition. It is also available as part of legacy IDS embedded edition for older FPGA device families like Spartan®-6, Virtex®-6 etc.
LEON3 is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The processor is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs. The full source code is available from Aeroflex Gaisler AB under the GNU GPL license, allowing free and unlimited use for research and education. LEON3 is also available under a low-cost commercial license, allowing it to be used in any commercial application at a fraction of the cost of comparable IP cores. A fault-tolerant version (LEON3-FT) is available for System Critical applications.
A dual-core ARM® Cortex™-A9 MPCoreTM processor is the heart of the Cyclone® V SoC, Arria® V SoC, and Arria® 10 SoC. All three devices make use of the same high performance processor, but with increased clock speeds and performance in the Arria V SoC and even moreso in the Arria 10 SoC. Because the three devices use essentially the same processor, the Cyclone V SoC can effectively be used for early prototyping and software development for systems based on any of the three SoC variants.
UVVMUVVM is a VHDL testbench Infrastructure, Architecture, Library and Methodology for making better VHDL tesbenches.
Register WizardBitvis provides a tool to accelerate and optimize the design flow for handling register interfaces between software and hardware.
Bitvis MethodologyOur methodology in FPGA design and verification has evolved for more than a decade.
Bitvis coursesBitvis holds FPGA related on-site or open courses on a regular basis.
We can help with
It all starts with the system design and by breaking the individual tasks down to subtasks and make the best tradeoff between a maintainable system containing a structured overview, and on the other side, make a highly optimised design to serve specific task and timing critical tsks. We recommend to maintain the structured top level architecture at all time and only for timing critical applications, do functional adaption where code might be difficult to understand in the maintenance perspective. Most designs will undergo a number of iterations with additional features and development. Spend time again and again to catch up with a messy architecture will quickly become very expensive as well as being a high risk of introducing errors during maintenance.
Linux is not realtime and users should not expect Linux to be a realtime. For such trasks choose another operating system or make a dedicated hardware front end in the FPGA. It´s generally not advised to change or tweak the Linux kernel to gain more realtime performance. It is possible to optimise the scheduler in certain ways make Linux more responsive to certain tasks. It is also possible to install a dedicated realtime patch of Linux, but our tests have revealed weakness with the realtime patch as well. Real this article... link here.
It´s a paradox that most System on Chip isn´t really a complete system, but a package of combined functionality containing both a dedicated CPU and an FPGA which is tied together on the same die. The benefit is usually higher clock speed and lower power supply for certain functions, but these devices will in most cases connect to external flash, external RAM, with various timing constraints as well as the application specific I/O adoption. In these cases we will need to modify the BSP shipped with the SoC circuit to fit the external architecture.
Most customers would like the ability to do field upgrade and most chip vendors support such functions through specific IP. The IP must however in most cases be encapsulated with customised software to fit into our clients applications which is exactly what we do for most projects.
Preloader and U-boot is standard ways to load Linux. There is initially no difference in the preloader and U-boot procedure between a stand alone CPU and a SoC. Preloader can be started from USB interface, from a memory card or from the network. We have however for some applications twisted this al little and started the preloader from the FPGA. Then laounching U-Boot to install Linux and finally in the standard boot mode controlling boot sequence from the FPGA.
U-boot can be launched from various medias like SD-card , Ethernet, Flash and more once the interface has been set up properly.
Many features can be solved eiter in a CPU or through dedicated hardware. A top down approach, from system level to down, will in most cases appear to provide the best overview while maintaining flexibility in the project. Breaking each task down to sub-tasks will help reveal what kind of hardware resources are required to solve the task. To the extent that you are able to factorize the tasks, you will be able to reuse function blocks for multiple tasks. It´s part of our culture to continuously develop tool which will help to speed up and streamline the entire development process. Register Wizard is such a tool which through a single source JSON file will generate the entire register interface including header files, documentation, VHDL files for the entire processor interface, and a VHDL based testbench for the FPGA.
In orded to increase the Realtime characteristics, it might be more efficient to set up two different operating systems on 1+1 processor cores rather than running the same OS on multiple cores. FreeRTOS is a great realtime OS when set up to handle only the realtime tasks. Embedded Linux can then be set up to handle all HMI and advanced communication on the other core.