All publications

Public or On-site course on request Advanced VHDL Verification – Made simple. Date: TBD Time of day:  9:00-16:30/17:00 (TBD) Language: English Place:   Public or On-site Course fee: To be agreed Course responsible: Espen Tallaksen, Bitvis AS     (Mobile: +47 934 … Read More

Advanced VHDL Verification – Made simple. Date: 5-7 May 2020  (3 days) Time of day:  9:00-16:30/17:00 (TBD) Language: English Place:   Berlin, Germany Registration fee: EUR 1850 +VAT Course responsible: Espen Tallaksen, Bitvis AS     (Mobile: +47 934 21 277) Registration: … Read More

Advanced VHDL Verification – Made simple. Date: November 24-26, 2020  (3 days) Time of day:  9:00-16:30/17:00 (TBD) Language: English Place:   Munich, Germany Registration fee: EUR 1850 +VAT Course responsible: Espen Tallaksen, Bitvis AS     (Mobile: +47 934 21 277) Registration: … Read More

Advanced VHDL Verification – Made simple. A general introduction to modern verification methodology and to UVVM – as the fastest growing FPGA and ASIC verification methodology in Europe. (26% of all FPGA designers in Europe pr. May 2018 – and … Read More

Advanced VHDL Verification – Made simple. Date: November 12-14, 2019  (3 days) Time of day:  9:00-16:30/17:00 (TBD) Language: English Place:   Stuttgart, Germany Registration fee: EUR 1850 +VAT Course responsible: Espen Tallaksen, Bitvis AS     (Mobile: +47 934 21 277) Registration: … Read More

Advanced VHDL Verification – Made simple. Date: June 18-20, 2019  (3 days) Time of day:  9:00-16:30/17:00 (TBD) Language: English Place:   Copenhagen, Denmark(at Circle Consult in Nærum, Rundforbivej 271A) Registration fee: EUR 1850 +VAT(for multiple participants from the same company: … Read More

Advanced VHDL Verification – Made simple. Date: November 13-15, 2018  (3 days) Time of day:  9:00-16:30/17:00 Language: English Place: Scandic Hotel Asker Asker (just outside Oslo), Norway Registration fee: NOK 19.000 (for multiple participants from the same company: 2nd: NOK 18.000, … Read More

Artikkel: https://www.ffi.no/no/Aktuelle-tema/Sider/God-tur-til-Mars.aspx – Det vil få oppmerksomhet over hele verden når resultatene fra den røde planeten begynner å komme inn, sier forsvarsminister Frank Bakke-Jensen. ​Onsdag kom forsvarsministeren til Kjeller for å feire en norsk teknologibragd. Bakkeradaren Rimfax er en av … Read More

Advanced VHDL Verification – Made simple. Date: November TBD, 2018  (3 days) Time of day:  9:00-16:30/17:00 Language: English Place:   Ankara, Turkey Registration fee: TBD Course responsible: Espen Tallaksen, Bitvis AS     (Mobile: +47 934 21 277) Registration: TBD Deadline for … Read More

Advanced VHDL Verification – Made simple. Date: October 2-4, 2018  (3 days) Time of day:  9:00-16:30/17:00 Language: English Place: Stockhom, Sweden Registration fee: SEK 19.000 (for multiple participants from the same company: 2nd: SEK 18.000, 3rd: SEK 17.000, 4th: SEK 16.000, … Read More

Advanced VHDL Verification – Made simple. Date: June 19-21, 2018  (3 days) Time of day:  9:00-16:30/17:00 Language: English Place:   Munich, Germany Registration fee: EUR 1850 +VAT Please see TRIAS course site Course responsible: Espen Tallaksen, Bitvis AS     (Mobile: +47 … Read More

Intel Cyclone 10 LP FPGAs are designed for low static power, low cost applications, such as I/O expansion, sensor fusion, motor/motion control, chip-to-chip bridging and IoT applications. Read more here

This article explores the use of the kernel configuration Adaptive Ticks, combined with the patch RT-Preempt, for improving real-time performance in Linux. Tests reveal that enabling adaptive ticks on a kernel patched with RT-Preempt does not work. Additionally, increased latencies … Read More

IT konsulentselskapet, Acando Norge, kjøper alle aksjene i selskapet Bitvis AS. Kontrakten ble signert 15. september og vil tre i kraft fra 1. oktober. Bitvis vil med dette bli et heleid datterselskap av Acando, men vil fortsette å operere som … Read More

  Date: Oct 31 – Nov 2, 2017  (3 days) Time of day:  9:00-16:30/17:00 Language: English Place:   Ankara, Turkey http://www.demorahotel.com.tr/ Registration fee: EUR 1900 +VAT Course responsible: Ates Berna +90 216 9120167 Registration: To info@electraic.com Deadline for registration: 13 October … Read More

Date: Oct 24-25, 2017  (2 days) Time of day:  9:00-16:30/17:00  (TBD) Language: English Place:   Munich, Germany Registration fee: EUR 1250 +VAT,   Please see TRIAS course site Course responsible: Espen Tallaksen, Bitvis AS     (Mobile: +47 934 21 277) Registration: … Read More

Advanced VHDL Verification – Made simple. Date: Nov 28-30, 2017  (3 days) Time of day:  9:00-16:30/17:00 Language: English Place:   TBD, Germany (TRIAS will come up with location soon) Registration fee: EUR 1850 +VAT Please see TRIAS course site Course … Read More

FPGAworld 2017 in Stockholm Sept. 19, Copenhagen Sept. 21. Bitvis will give a presentation in the industrial track: Constrained Random and Functional Coverage for VHDL testbenches – controlled in a structured manner by Espen Tallaksen Full Program for Stockholm Full … Read More

ESA på jakt etter bedre verifikasjonsplattformer for FPGA: Velger å fullfinansiere neste utviklingstrinn i norske Bitvis’ verifikasjonsverktøy UVVM. Limet i avtalen var Norsk Romsenter. http://elektronikknett.no/Artikkelarkiv/2017/September/ESA-satser-paa-norsk-verifikasjonssystem

FPGA-forum er den årlige møteplassen for FPGA-miljøet i Norge. Her samles FPGA-designere, prosjektledere, tekniske ledere, forskere, siste års studenter og de største leverandørene på ett sted for 2 dagers praktisk fokus på FPGA. Det blir foredrag fra norske bedrifter om … Read More

We are very happy to welcome David Kristiansen as embedded software developer in Bitvis AS. The company has now 7 embedded software developers and 11 FPGA designers.

Our 2-day ‘Accelerating FPGA design’ followed by our 3-day ‘Advanced VHDL verification – Made simple’ was presented for Satellogic in Buenos Aires during 4 long and intensive days. It was a an enthusiastic audience, – normally making impressing satellite-systems with … Read More

Av: Bjørn Ø Andersen “SSVConference ble arrangert på Telenor Arena 4.-6. april i år. Elektronikks utsendte var på en rask tur første utstillingsdag. Det var mest aktivitet rundt konferansene.” William Braathen t.v, Espen Tallaksen t.h. Elektronikk eMagasin 04 / 2017 … Read More

Space X, Falcon 9 rocket was launched successfully yesterday evening. This event represents a milestone in modern Space technology – being the first reused stage from an earlier flight. The Satellite manufacturer for SES-10 is Airbus Defense and Space, where … Read More

Av: Håvard Solerød “Når satellitten Solar Orbiter Skytes opp i rommet neste år, er det et norsk selskap i Asker som skal sikre at dette enestående prosjektet til syv milliarder kroner ikke smelter i møte med sola.” Vi menn UKE … Read More

In Oslo, March 7-9

Stor oppslutning og opptur for Bitvis. t.v. Daniel H. Blomkvist

Av: Bjørn Ø Andersen “Asker bedriften har deltatt i en rekke romfartsprosjekter de siste årene. Snart har de “vært” på alle planetene fro Solen til Jupiter. – Det gir et ekstra kick å jobbe med sånt, innrømmer de.” Elektronikk eMagasin … Read More

Software and FPGA developers often struggle with synchronization of the register map. Parallel register access from multiple software applications is also a difficult issue to deal with. Auto generation of code from a single source keeps the register map synchronized. … Read More

Accelerating FPGA Design Learn how basic quality improvement will also reduce development time and allow efficient reuse. It’s all about architecture, structure and pitfall prevention. This is an extended Design part of what was previously “FPGA Development Best Practices” Date: … Read More

Bilde: Håvard Solerød/tu.no “I bane rundt sola: Bitvis i Asker har utviklet styresystemet for solpanelet som henter inn strøm til ESA-satellitten Solar Orbiter. Arbeidet er komprimert på en FPGAer brikke.” tu.no 30. DES. 2016 – 09:40

Design and verification conference and exhibition in Munich, Germany – October 2016 https://dvcon-europe.org/   DVCon Europe 2017 is a technical conference in Europe targeting the application of standardized languages, tools, and methodologies for the design and verification of electronic systems … Read More

“it may sound disappointing, but the Linux operating system is not an RTOS. This article focus on some aspects of interrupt handling in Linux kernel related to real-time performance.

Foto: Elin Svilaas, NCE SE – 15-09-2016 “Salgsdirektør William Braathen (t.h) i medlemsbedriften til NCE Systems Engineering, Bitvis, forteller hvordan selskapet løser design av mikroelektronikk for space til Lars Bjærtnes i Physical design. Over dem ser vi en satellitt-modell av … Read More

FPGAworld 2016 in Stockholm Sept. 13 Bitvis will give a presentation in the industrial track in Stockholm: Verifying corner cases in a structured manner – using VHDL Verification Components (VVC) UVVM provides overview, readability, maintainability and reuse for medium to … Read More

Learn to reduce development time and allow efficient reuse. This course will be held in cooperation with Realtime Embedded (Stockholm) (for adminstrative issues in Sweden). This course is about improving Digital design, Architecture and Ccoding for FPGA & ASIC – … Read More

We are very happy to welcome Marius Elvegård as FPGA developer in Bitvis AS. We are now 6 embedded software developers and 10 FPGA designers.

is one of the largest FPGA conferences in the world. We are really proud that two presentations and a tutorial have been accepted, and this only 5 months after releasing UVVM VVC Framework  🙂 Bitvis will have two presentations and … Read More

Av: Einar Karlsen “Hos utviklingsbedriften Bitvis, som er kjent for sitt fokus på designmetodikk og kodekvalitet, nikkes det anerkjennende når de hører om den nye læringsmetoden ved Universitetet i Agder. Metodikk ansvarlig: Michal Koziel.” Elektronikk eMagasin 06 / 2016 – … Read More

Av: Einar Karlsen – 01-06-2016 09:45 “Standplass koster penger, og det gjelder å utnytte plassen. Det synes vi Bitvis AS hadde gjort, med godt synlige satellitter som svevde over hodene deres, og visning av spennende prosjekter på storskjerm. En gullbelagt … Read More

Arild Reiersen, our 11th FPGA designer, sends a warm welcome to new colleagues in Bitvis. A team passionate about structured development and verification in FPGA, Embedded Software development and System On Chip design. Now counting 20 employees. More details soon … Read More

Av: Einar Karlsen “Ethernet er på vei inn i stadig flere anvendelser. Norske Transpacket kan bidra til å løse flaskehalser i fremtidens 5G-nett og bilelektronikk med sin deterministiske IP. -Utviklingsmetodikken i bunn er særdeles vikitig. – På dette området har … Read More

‘Acclerating FPGA VHDL Verification’ was our first pure FPGA Verification course, based on ‘FPGA Development Best Practices’, and for the first time with labs – as we go through UVVM in sufficient detail for the participants to make their own … Read More

– Including UVVM Utility Library and VVC Framework Efficiency and quality is all a question of overview, readability, maintainability and re-use, – and UVVM is the answer. A description of the course and related info can be found *HERE* Please note that … Read More

Av: Einar Karlsen “Bitvis i Asker har etablert seg som et robust utviklingssenter i Norge, og tilbyr i tillegg til utviklings- og programmeringstjenester, hjelpemidler for verifikasjon og utvikling av testbenker”   Elektronikk eMagasin 03 / 2016 – side 10

Our 2-3 day course ‘FPGA Development Best Practices’ is now split into separate courses on Design and Verification: – Accelerating FPGA Design (Digital Design; language, tool and technology independent ) – Accelerating FPGA VHDL Verification (Structured verification with examples from UVVM) The purpose of this … Read More

NCE Systems Engineering ønsker Bitvis AS velkommen som ny medlemsbedrift. Bitvis er et designsenter med spesiell kompetanse innen Embedded Software og FPGA. http://nce-se.no/index.php/nyheter/bitvis_nytt_medlem

Av: Einar Karlsen “Elektronikkdesignere kommer ut fra universitetene med altfor dårlig kunnskap om designmetodikk og -struktur. Industrien er ikke i stand til å tette dette kompetansehullet på egen hånd sier Espen Tallaksen.”   Elektronikk eMagasin 12 / 2015 – side … Read More

Av: Einar Karlsen “I slutten av oktober gikk den internasjonale konferansen NORCAS 2015 av stabelen i Oslo. Norske Bitvis benyttet anledningen til å kaste inn en brannfakkel om utdanningstilbudet. Det var mest aktivitet rundt konferansene.”   Elektronikk eMagasin 11 / … Read More

The following presentations will be given in Bergen Monday Sept. 28, 2015. (at Bergen University College). In the morning – a Guest lecture – primarily for students at University of Bergen and Bergen University College, but also open for FPGA … Read More

Bitvis is again giving technical presentations at FPGAworld (2015) – in Stockholm Sept. 8 – in Copehagen Sept. 10   ——- Bitvis will give the following presentation in the industrial track: ‘The critically missing VHDL testbench feature – Finally a … Read More

Verification is 51% of total FPGA development time (cf ‘Functional Verification Study’ from Wilson Research Group). Even more for control or protocol oriented design. Ignore this and you will iterate forever in the lab and suffer from bad product quality. … Read More

The purpose of a testbench (TB) is to check the behaviour of your DUT (Device Under Test). This really goes without saying, – but sometimes stating the obvious is really needed. For any testbench you always provide stimuli and check … Read More

  An FPGA is programmable hardware and yields an extreme performance for time critical operations. Throughput and latency are magnitudes better than software solutions due to the massive parallelism of real hardware. FPGAs are basically the best of both worlds; … Read More

Free verification seminar for simple and advanced verification Our Free & Open source, Bitvis Utility Library (BVUL) was released two years ago accompanied by a free, one time only introduction seminar – with very good attendance. The library is now … Read More

Copenhagen, Denmark: Location TBD Date: March 24-26, 2015 Time of day: Tues: 10:00-16:30,   Wedn: 9:00-16:30,   Thur: 8:30-15:30 Language: The course will be held in English. All slides are in English Place: TBD Registration fee: DKK 15.600 (Discount for … Read More

“it may sound disappointing, but the Linux operating system is not an RTOS. This article focus on some aspects of interrupt handling in Linux kernel related to real-time performance. By Michal Koziel Link to PDF  

Av: Einar Karlsen – 11-12-2014 10:15 “Ifølge adm. direktør Espen Tallaksen hos Bitvis har selskapet over lengre tid vært på utkikk etter en salgsmann med sterk teknisk bakgrunn. Nå har de endelig funnet ham, og William Braathen er tilsatt som … Read More

Generic programming is about writing your code portable, modular and easily maintainable. There are however limits for how much effort you want to put into making your code generic. This article will give an overview of different levels of genericity … Read More

UVM (and SystemVerilog) are new buzzwords within advanced ASIC verification, but are often mentioned also for FPGA verification. There is no doubt that verification is a major and increasing challenge for FPGA development, but for most FPGA projects UVM is … Read More

– Sometimes you want to see what has actually happened in a simulation – Sometimes you want to see whether you have covered all functional aspects of your design – Sometimes you want to see the various accesses made on … Read More

Using a virtual machine (VM) as a development platform for embedded software has many advantages. VMs enable better portability, greater redundancy, lower setup- and recovery times. The ability to archive the entire development environment allows better control over software packages … Read More

The way you implement your FPGA design and write your code has a huge impact on your development efficiency and product quality. The strange thing is that even many experienced designers tend to write both bad and ugly code. Does … Read More

Most simple testbenches have close to no structure, are terrible to modify and hopeless to understand. They often take far too much time to implement, and provide close to no support when debugging potential problems. A general solution to this … Read More

Phasellus porta, nibh quis viverra posuere, lectus dui consectetur purus, in placerat nisi orci eget dui. Fusce cursus sapien urna, at sollicitudin sapien sagittis non. Aenean suscipit scelerisque nibh at gravida. Vivamus pretium urna eu quam eleifend, eu fringilla purus … Read More

Phasellus porta, nibh quis viverra posuere, lectus dui consectetur purus, in placerat nisi orci eget dui. Fusce cursus sapien urna, at sollicitudin sapien sagittis non. Aenean suscipit scelerisque nibh at gravida. Vivamus pretium urna eu quam eleifend, eu fringilla purus … Read More

Phasellus porta, nibh quis viverra posuere, lectus dui consectetur purus, in placerat nisi orci eget dui. Fusce cursus sapien urna, at sollicitudin sapien sagittis non. Aenean suscipit scelerisque nibh at gravida. Vivamus pretium urna eu quam eleifend, eu fringilla purus … Read More

Some of the most important quality aspects of an FPGA are: a) Functional quality. Does the FPGA perform its intended tasks – for all corner cases – and with no hiccups? b) Ease of modification. How easy is it to … Read More

Av: Espen Tallaksen “God verifikasjon er kritisk for kvaliteten på en FPGA og dermed også sluttproduktet. Strukutrert verifikasjon er kritisk for tidsbruken, men også som et grunnlag for god verifikasjon og debugging. Det første som må på plass er en … Read More

Most companies have a strong focus on coordinating company critical processes, like sales, marketing, accountancy, department management, QA, etc. Lots of companies have also understood that project management is equally critical, but why is the development methodology treated so differently? … Read More

Many designers and project managers consider efficiency on one hand and quality and modifiability on the other hand to be inverse proportional. In other words improving the quality/modifiability has an efficiency penalty, and improving the efficiency results in lowering the … Read More

Av Espen Tallaksen “Det er ingen tvil om at det har skjedd enorme forbedringer innen FPGA-utvikling de siste årene, men på noen kritiske områder har verden nesten stått stille. Store deler av en FPGA kan i dag settes sammen nesten … Read More

Av: Einar Karlsen “Det nyetablerte teknologiselskapet Bitvis AS har målsetting om å bli det ledende designsenteret for innvevd programvare og FPGA i Norge. Med seg har de en klokketro på at god designmetodikk sikrer både bedre kvalitet og effektivitet i … Read More