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Advanced VHDL Verification – Made simple. Date: 5-7 May 2020  (3 days) Time of day:  9:00-17:00 CEST Language: English Place:   Live Online (see below) Registration fee: EUR 1850 +VAT Course responsible: Espen Tallaksen, Bitvis AS     (Mobile: +47 934 21 … Read More

Advanced VHDL Verification – Made simple. NOTE: This course is now changed to a Live Online course due to the current pandemic:  Date: 5-7 May 2020  (3 days) Time of day:  9:00-16:30/17:00 (TBD) Language: English Place:   Berlin, Germany Registration … Read More

Advanced VHDL Verification – Made simple. Date: November 24-26, 2020  (3 days) Time of day:  9:00-16:30/17:00 (TBD) Language: English Place:   Munich, Germany Registration fee: EUR 1850 +VAT Course responsible: Espen Tallaksen, Bitvis AS     (Mobile: +47 934 21 277) Registration: … Read More

Advanced VHDL Verification – Made simple. A general introduction to modern verification methodology and to UVVM – as the fastest growing FPGA and ASIC verification methodology in Europe. (26% of all FPGA designers in Europe pr. May 2018 – and … Read More

Advanced VHDL Verification – Made simple. Date: November 12-14, 2019  (3 days) Time of day:  9:00-16:30/17:00 (TBD) Language: English Place:   Stuttgart, Germany Registration fee: EUR 1850 +VAT Course responsible: Espen Tallaksen, Bitvis AS     (Mobile: +47 934 21 277) Registration: … Read More

Advanced VHDL Verification – Made simple. Date: June 18-20, 2019  (3 days) Time of day:  9:00-16:30/17:00 (TBD) Language: English Place:   Copenhagen, Denmark(at Circle Consult in Nærum, Rundforbivej 271A) Registration fee: EUR 1850 +VAT(for multiple participants from the same company: … Read More

Advanced VHDL Verification – Made simple. Date: November 13-15, 2018  (3 days) Time of day:  9:00-16:30/17:00 Language: English Place: Scandic Hotel Asker Asker (just outside Oslo), Norway Registration fee: NOK 19.000 (for multiple participants from the same company: 2nd: NOK 18.000, … Read More

Artikkel: https://www.ffi.no/no/Aktuelle-tema/Sider/God-tur-til-Mars.aspx – Det vil få oppmerksomhet over hele verden når resultatene fra den røde planeten begynner å komme inn, sier forsvarsminister Frank Bakke-Jensen. ​Onsdag kom forsvarsministeren til Kjeller for å feire en norsk teknologibragd. Bakkeradaren Rimfax er en av … Read More

Advanced VHDL Verification – Made simple. Date: November TBD, 2018  (3 days) Time of day:  9:00-16:30/17:00 Language: English Place:   Ankara, Turkey Registration fee: TBD Course responsible: Espen Tallaksen, Bitvis AS     (Mobile: +47 934 21 277) Registration: TBD Deadline for … Read More

Advanced VHDL Verification – Made simple. Date: October 2-4, 2018  (3 days) Time of day:  9:00-16:30/17:00 Language: English Place: Stockhom, Sweden Registration fee: SEK 19.000 (for multiple participants from the same company: 2nd: SEK 18.000, 3rd: SEK 17.000, 4th: SEK 16.000, … Read More

Advanced VHDL Verification – Made simple. Date: June 19-21, 2018  (3 days) Time of day:  9:00-16:30/17:00 Language: English Place:   Munich, Germany Registration fee: EUR 1850 +VAT Please see TRIAS course site Course responsible: Espen Tallaksen, Bitvis AS     (Mobile: +47 … Read More

Intel Cyclone 10 LP FPGAs are designed for low static power, low cost applications, such as I/O expansion, sensor fusion, motor/motion control, chip-to-chip bridging and IoT applications. Read more here