Development Efficiency – For Technical Managers

This course is targeted at Technical managers, Project managers and and other decision makers who are involved in making electronic (embedded) systems with one or more FPGAs. Focus in this course will be quality, efficiency, schedule estimation, cost, TTM and LCC for managers with a technical background (general understanding of electronic systems), but not necessarily any detailed knowledge on FPGAs.

 

At Course Completion

You will be aware of:

  • Elements of risk in the FPGA development
  • Product quality risks when developing an FPGA
  • How to reduce risks and improve efficiency

 

Presenter

espen-tallaksen-course-sqr

    • Espen Tallaksen, managing director and founder of Bitvis AS
    • 30 years of experience within VHDL design and verification
    • During twenty years Espen has had a special interest for methodology cultivation and pragmatic efficiency and quality improvement. One result of this interest is the UVVM verification platform that is currently being used by companies world-wide.
    • He has given many presentations in Scandinavia on various technical aspects of FPGA development — including: – Keynote at FPGAworld – Keynote speaker at ABB Embedded Systems Forum – Various presentations at FPGAworld…and many more
    • Initiator and chair of the Norwegian FPGA-forum committee

 

Bitvis AS

The extended history…

  • Bitvis was established in 2012 to provide state of the art design services within FPGA development and embedded Software development
  • The story goes all the way back to Digits founded in 2003 which was later acquired and where as a splinter group with the inherited spirit of Digitas AS founded Bitvis AS.
  • Espen Tallaksen has ever since the foundation of Digitas in 2003 held courses and seminars as open class, for companies or as lectures for local universities – all in the aim to make VHDL development more efficient and with higher quality.
  • Courses have so far been held in Norway, Sweden, Denmark, Germany and UK.

 

Agenda

These issues are the main subjects of this course:
(See one course example here: /events/accel-fpga-verifi,-berlin-2016/)

  • Making a simple VHDL test bench step-by-step

 

Prerequisites

None

Skills Required

  • Some prior knowledge within electronics development