2 Days VHDL Verification Course with hands on tutorials

VHDL 2008 has introduced a number of functions that have enabled VHDL to become a more powerfull verification platform. Bitvis has developed a structured tool – a verification component framework that makes verification simple and straight forward – even for complex designs. This course will cover general verification methodology with reference to UVVM Utillity Library and VVC Framework.


At Course Completion

You will be able to:

  • Structure an FPGA-verification platform
  • Improve your general working methodology
  • Understand the terms: coverage, debugging, randomization
  • Implement your testbench and use the test sequencer
  • Set up and use the UVVM framework
  • Have the complete UVVM, VHDL based verification platform with you
  • Develop and use Bus Functional Models (BFM)
  • Develop and use VHDL Verification Components (VVC)
  • Reuse and modify BFMs and VVCs with a minimum of effort
  • See how the UVVM framework increases overview, readability and maintainability
  • Reduce time for verification significantly




    • Espen Tallaksen, managing director and founder of Bitvis AS
    • 30 years of experience within VHDL design and verification
    • During twenty years Espen has had a special interest for methodology cultivation and pragmatic efficiency and quality improvement. One result of this interest is the UVVM verification platform that is currently being used by companies world-wide.
    • He has given many presentations in Scandinavia on various technical aspects of FPGA development — including: – Keynote at FPGAworld – Keynote speaker at ABB Embedded Systems Forum – Various presentations at FPGAworld…and many more
    • Initiator and chair of the Norwegian FPGA-forum committee


Bitvis AS

The extended history…

  • Bitvis was established in 2012 to provide state of the art design services within FPGA development and embedded Software development
  • The story goes all the way back to Digits founded in 2003 which was later acquired and where as a splinter group with the inherited spirit of Digitas AS founded Bitvis AS.
  • Espen Tallaksen has ever since the foundation of Digitas in 2003 held courses and seminars as open class, for companies or as lectures for local universities – all in the aim to make VHDL development more efficient and with higher quality.
  • Courses have so far been held in Norway, Sweden, Denmark, Germany and UK.



These issues are the main subjects of this course:
(See one course example here: /events/accel-fpga-verifi,-berlin-2016/)

  • Making a simple VHDL test bench step-by-step
  • Using procedures and making good BFMs
  • Applying logs, alerts, value and stability checkers, awaits, etc…
  • Making an advanced VHDL test bench step-by-step
  • Assertions, randomisation, constrained random, coverage, debuggers, monitors
  • Verification components and testbench architecture for advanced Verification
  • Making testbenches as simple as possible – adapting to the DUT complexity
  • Structuring, Debugging, Overview, Maintainability, Extendibility
  • Examples and labs using UVVM



We recommend reading the following linked posts:



Skills Required

  • Some prior knowledge and use of VHDL
  • Background in digital logic design
  • Understanding of synthesis and simulation processes


Applicable Training Curriculum

This course is a based on the verification part of ‘FPGA Development Best Practices’, but extended with more subjects, details and lots of labs.

A description of the course can be found *** HERE ***