2-days course for both really experienced and less experienced designers
This course is packed with relevant and pragmatic Best Practices for FPGA development. It is complementary to the courses for tools, technologies, design/verification languages and digital design from Altera, Xilinx, Aldec, Mentor, Esperan, Doulos, etc. They all have excellent courses for their targets, but our course is unique in its focus on design practices for better quality products and more efficient projects.
At Course Completion
You know more about:
- How to make an Architecture with better structure
- Typical coding issues
- Verification and creating a testbench
- How safely handle clock domain crossing
- How to handle reset signalsli>
- Quality Assurance – at the development level
- Espen Tallaksen, managing director and founder of Bitvis AS
- 30 years of experience within VHDL design and verification
- During twenty years Espen has had a special interest for methodology cultivation and pragmatic efficiency and quality improvement. One result of this interest is the UVVM verification platform that is currently being used by companies world-wide.
- He has given many presentations in Scandinavia on various technical aspects of FPGA development — including: – Keynote at FPGAworld – Keynote speaker at ABB Embedded Systems Forum – Various presentations at FPGAworld…and many more
- Initiator and chair of the Norwegian FPGA-forum committee
This well established course (previously from Digitas) has been held in DK, SE and NO several times – with very good feedback from the participants (from both really experienced and less experienced designers).
The extended history…
- Bitvis was established in 2012 to provide state of the art design services within FPGA development and embedded Software development
- The story goes all the way back to Digits founded in 2003 which was later acquired and where as a splinter group with the inherited spirit of Digitas AS founded Bitvis AS.
- Espen Tallaksen has ever since the foundation of Digitas in 2003 held courses and seminars as open class, for companies or as lectures for local universities – all in the aim to make VHDL development more efficient and with higher quality.
- Courses have so far been held in Norway, Sweden, Denmark, Germany and UK.
The total course has the following approximate split on main subjects (Mainly language independent, but examples are shown for VHDL):
- 35% Design – architecture, structure, issues, coding
- 25% Verification – architecture, structure, methodology
- 20% Clocking, Clock Domain crossing, Resets and Timing
- 10% Reuse and design for reuse
- 10% Quality assurance – at the development level
- Verification components and testbench architecture for advanced
Our presentation from FPGAworld and FPGA-forum on ‘Bugs and Problems – Worst disasters’ (now called ‘Backgrounder for….’) gives a good introduction to why some Best Practices are in deed very important for quality and efficiency.
- Some prior knowledge and use of VHDL
- Background in digital logic design
- Understanding of synthesis and simulation processes
Applicable Training Curriculum
Note that a 3-day version is also possible. This would have additional presentations on design, coding and quality issues.
See also the result of the written feedback (evaluation form) from our course in Stockholm Nov. 19-20, 2014, with 15 participants from Sweden, Denmark and Norway.