Design and verification conference and exhibition in Munich, Germany – October 2016 https://dvcon-europe.org/
UVVM @ DVCon-Europe *** – On my way to Munich to present a 90-minute tutorial on ‘UVVM – A game changer for FPGA VHDL Verification’ tomorrow. – Espen
DVCon Europe 2017 is a technical conference in Europe targeting the application of standardized languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. Hosted by Accellera Systems Initiative, the format of DVCon Europe 2017 is similar to the successful DVCon United States conference held for over 20 years in the Silicon Valley.