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Improve your VHDL testbench – A practical approach (Presented @FPGA World 2013)

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Most simple testbenches have close to no structure, are terrible to modify and hopeless to understand. They often take far too much time to implement, and provide close to no support when debugging potential problems. A general solution to this problem was presented here by Digitas in 2009, and by Bitvis as an Aldec webinar in April 2013. (Please see bitvis.no/downloads) Bitvis Utility Library is now available as open source to support this solution. This allows a major improvement for most companies. This presentation goes beyond the webinar and presents the features, concept and usage of the library.