‘Acclerating FPGA VHDL Verification’ was our first pure FPGA Verification course, based on ‘FPGA Development Best Practices’, and for the first time with labs – as we go through UVVM in sufficient detail for the participants to make their own well structured testbenches.
The participants were given evaluation forms to fill in, and these were handled in full by our partner Realtime Embedded in Stockholm. The following average scores were obtained – on a scale from 1 (Very Dissatisfied) to 5 (Excellent):
|Technical aspects of the course||4.8|
|Presenter’s knowledge in his area of expertise||5.0|
|The relevance of the course contents||5.0|
|Does the course live up to your expectations||4.8|
|The educational material in the course||4.3|
|The location where the course was held||4.0|
|Overall impression of the course||4.7|
Average experience of the participants was 11 years, with min and max being 3 and 25 years respectively.
And very important to us as a course provider: All the participants would recommend this course to others 🙂