FPGAworld 2016 in Stockholm Sept. 13
Bitvis will give a presentation in the industrial track in Stockholm:
Verifying corner cases in a structured manner – using VHDL Verification Components (VVC)
UVVM provides overview, readability, maintainability and reuse for medium to high complexity VHDL testbenches. Key enablers are a structured architecture, an easily readable test sequencer and fast VVC development. This presentation will explain the concept, show how easy value and cycle related corner cases can be targeted, and how constrained random, coverage and efficient debugging is supported.
UVVM is a true game changer with great feedback from the VHDL community, – and gaining momentum.