Our 2-3 day course ‘FPGA Development Best Practices’ is now split into separate courses on Design and Verification:
The purpose of this change is to allow the course participants to choose on or the other, which is particularly important for ASIC designers using Verilog or SystemVerilog for verification. They can now attend the language neutral design course (FPGA and ASIC have the same issues), whereas most of the FPGA community can attend both.
The verification course is extended with labs using UVVM Utility Library and VVC Framework.
Both courses are continuously updated – in particular on issues with great importance for efficiency and quality.
First new courses will be in Stockholm 20-21 April and 8-9 June. Click on the links above for information.