Events

Advanced VHDL Verification – Made simple. A general introduction to modern verification methodology and to UVVM – as the fastest growing FPGA and ASIC verification methodology in Europe. (26% of all FPGA designers in Europe pr. May 2018 – and … Read More

Advanced VHDL Verification – Made simple. Date: November 12-14, 2019  (3 days) Time of day:  9:00-16:30/17:00 (TBD) Language: English Place:   Stuttgart, Germany Registration fee: EUR 1850 +VAT Course responsible: Espen Tallaksen, Bitvis AS     (Mobile: +47 934 21 277) Registration: … Read More