Advanced VHDL Verification – Made simple. Date: November TBD, 2018 (3 days) Time of day: 9:00-16:30/17:00 Language: English Place: Ankara, Turkey Registration fee: TBD Course responsible: Espen Tallaksen, Bitvis AS (Mobile: +47 934 21 277) Registration: TBD Deadline for … Read More
Advanced VHDL Verification – Made simple. Date: October 2-4, 2018 (3 days) Time of day: 9:00-16:30/17:00 Language: English Place: Stockhom, Sweden Registration fee: TBD Course responsible: Espen Tallaksen, Bitvis AS (Mobile: +47 934 21 277) Registration: TBD Deadline for … Read More