Universal VHDL Verification Methodology
UVVM is a VHDL testbench infrastructure, Architecture, Library and Methodology for making better VHDL tesbenches. UVVM is used world wide to speed up verification and improve the overall FPGA design quality. Applicable for both FPGAs and ASICs.
Advanced verification framework
A good test harness architecture is key to Overview, Understanding, Maintainability, Simplicity, Extensibility and Reuse, - and of course then to a much verification and better product quality.
For simple verification scenarios, you only need a simple testbench and Utility Library, but as soon as have a slightly more advanced design you really also need a good testbench architecture.
UVVM is lego-like and easily understandable even by a SW or HW designer.
The alternative to UVVM’s test harness architecture is often either a slightly chaotic combination of multiple trigger signals, data and handshakes, or a system with a lot of inter process synchronization that initially looks good, but very soon becomes too much for a proper overview.
Please see ***** for a simple introduction (http://bitvis.no/media/21190/UVVM_Advanced_Verif_made_simple_1.pdf)
The verification components in UVVM are very well structured, and basically you have exactly the same architecture for all interfaces/protocols.
This also makes it really simple to make new VVCs based on your own BFMs. UVVM even provides a script to generate your new VVC, and all you have to do is just to add your own BFMs and commands.
Designers have always made their own verification modules/components, and on thing they have always struggled with is split transaction interfaces – like the Avalon MM.
In UVVM VVCs this is dead simple. All you have to do is just to insert a second pair of Queue and Executor, and suddenly you have an extremely well structured approach.
Another major advantage with the VVCs of UVVM is that all features are controlled the same way and it is easy to add and control extra functionality – like for instance a bit rate checker for a UART.
Having all verification functionality for a given interface/protocol inside one single VVC does of course also mean that you have the best and simplest reuse possible.
- Structured, LEGO-like test harness
- Allow simultaneous, multiple interface stimuli and checking
- Efficient reuse of Verification Components
- Semi automated generation of new VVCs
- Simple handling of split transactions (e.g. pipeline access)
- Simple encapsulation for a complete interface or protocol
- Allows VVCs instantiation even in the Design it self
- Logging and alert handling with verbosity control
- Quick References for UVVM and all included BFMs/VVCs
VHDL Verification Component
All VVCs share the same straight forward, self-explanatory and structured micro architecture, making it easy to develop new VVCs from an automatically generated template. It consists of three main parts: A Command Interpreter, a Command Queue and a Command Executor which will handle the interface protocol.