Tools and IP
To improve the quality and reduce the development time, Bitvis is continuously developing Tools and IP.
These Tools and IP allow Bitvis to perform a much better service for our customers, and they also make it possible for our customers to improve their own development projects.
Register Wizard generates code and documentation to be used in both FPGA and software development. This application generates: HDL files, software headers, testbenches, monitors, compile scripts and documentation from a single source.
UVVM Utility Library
UVVM Utility Library is a testbench infrastructure library and methodology for verifying FPGAs. This library provides fundamental support for logging, alert handling and result checking. Applying UVVM Utility Library results in a faster testbench development and efficient debug support.
UVVM VVC Framework
UVVM VVC Framework provides a FPGA verification environment with better overview, readbility and maintainability. It also increases the probability of detecting corner case design bugs. The tool supports constrained random stimuli, coverage verification and efficient verification reuse.