Advanced VHDL Verification – Made simple, * Live Online, 5-7 May 2020 (EMEA/APAC time zones)
Advanced VHDL Verification – Made simple. Date: 5-7 May 2020 (3 days) Time of day: 9:00-17:00 CEST Language: English Place: Live Online (see below) Registration fee: EUR 1850 +VAT Course responsible: Espen Tallaksen, Bitvis AS (Mobile: +47 934 21 … Read More