Advanced VHDL Verification – Made simple.
| Date: | November 12-14, 2019 (3 days) |
| Time of day: | 9:00-16:30/17:00 (TBD) |
| Language: | English |
| Place: | Stuttgart, Germany |
| Registration fee: | EUR 1850 +VAT |
| Course responsible: | Espen Tallaksen, Bitvis AS (Mobile: +47 934 21 277) |
| Registration: | If you received an invitation from Trias or first noticed this course on their web-site please register via them: see TRIAS course site. Otherwise please register to info@bitvis.no and give the following information: Name, Company name, Company Address, Email, Mobile, – and if required by your company a Purchase order reference. |
| Deadline for registration: | TBD. NOTE: Seating is limited, and priority will be given based on time of registration. |
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A description of the course can be found *** HERE ***