Advanced VHDL Verification – Made simple (Stockholm, Sweden) 2. Oct. 2018
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Advanced VHDL Verification – Made simple (Stockholm, Sweden) 2. Oct. 2018

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Advanced VHDL Verification – Made simple.

Date: October 2-4, 2018  (3 days)
Time of day:  9:00-16:30/17:00
Language: English
Place:   Stockhom, Sweden
Registration fee: TBD
Course responsible: Espen Tallaksen, Bitvis AS     (Mobile: +47 934 21 277)
Registration: TBD
Deadline for registration: TBD.
NOTE: Seating is limited, and priority will be given based on time of registration.

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A description of the course can be found *** HERE ***

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