Advanced VHDL Verification – Made simple.
A general introduction to modern verification methodology and to UVVM – as the fastest growing FPGA and ASIC verification methodology in Europe. (26% of all FPGA designers in Europe pr. May 2018 – and increasing)
|Date:||November 20-22, 2019 (3 days)|
|Time of day:|| Wedn+Thurs: 9:00-18:00. Friday: 9-15:00
(To allow easier travel)
(Thon Hotel Oslofjord in Sandvika, 12 min by train from Oslo). (Address)
|Registration fee:||NOK 19.000 (for multiple participants from the same company: 2nd: NOK 18.000, 3rd: NOK 17.000, 4th: NOK 16.000, 5th: NOK 15.000)|
|Course responsible:||Espen Tallaksen, Bitvis AS (Mobile: +47 934 21 277)|
|Registration:||To our course partners if you received the information from them.
Otherwise to firstname.lastname@example.org
Please provide the following info:
– Company info including invoice info
(Purchase order if that is required by your company)
– Company VAT registration number
– Names of participants
– E-mail address and Phone numbers to participants
– If applicable – Info on any special dietary requirements (for lunch)
|Deadline for registration:||18 November @ 2pm
NOTE: Seating is limited, and priority will be given based on time of registration.
A description of the course can be found *** HERE ***