Advanced VHDL Verification – Made simple.  – – – Course On Request
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Advanced VHDL Verification – Made simple. – – – Course On Request

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Public or On-site course on request

Advanced VHDL Verification – Made simple.

Date: TBD
Time of day:  9:00-16:30/17:00 (TBD)
Language: English
Place:   Public or On-site
Course fee: To be agreed
Course responsible: Espen Tallaksen, Bitvis AS     (Mobile: +47 934 21 277)
Public course?: Feel free to suggest a public course in your vicinity
On-site course?: Feel free to request an a course :
– in your office or nearby location
– for your company alone or also inviting others 

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A description of the course can be found *** HERE ***