Accelerating FPGA Design (Germany) 24. Oct. 2017
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Accelerating FPGA Design (Germany) 24. Oct. 2017

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Date: Oct 24-25, 2017  (2 days)
Time of day:  9:00-16:30/17:00  (TBD)
Language: English
Place:   Munich, Germany
Registration fee: EUR 1250 +VAT,   Please see TRIAS course site
Course responsible: Espen Tallaksen, Bitvis AS     (Mobile: +47 934 21 277)
Registration: Please see  TRIAS course site
Deadline for registration: NOTE: Seating is limited, and priority will be given based on time of registration.

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A description of the course can be found *** HERE ***

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