FEATURED PROJECTS
Advanced VHDL Verification – Made simple, * Live Online, 23-27 November 2020 (all days 08:30 to 12:30 CEST)
Advanced VHDL Verification – Made simple. Date: 23-27 September 2020 (5 days) Time of day: 08:30-12:30 CEST Language: English Place: Live Online (see below) Registration fee: EUR 1850 +VAT Course responsible: Espen... Read More
Accelerating FPGA Design Live Online, 16-19 November 2020 (all days 9:00-12:00 CEST)
Date: 16-19 November, 2020 (4 days) Time of day: 9:00-12:00 Language: English Place: Live Online Registration fee: EUR 1250 +VAT, Course responsible: Espen Tallaksen, Bitvis (Mobile: +47 934 21 277)... Read More
Advanced VHDL Verification – Made simple. – – – Course On Request
Public or On-site course on request Advanced VHDL Verification – Made simple. Date: TBD Time of day: 9:00-16:30/17:00 (TBD) Language: English Place: Public or On-site Course fee: To be agreed Course responsible:... Read More
Advanced VHDL Verification – Made simple, * Live Online, 5-7 May 2020 (EMEA/APAC time zones)
Advanced VHDL Verification – Made simple. Date: 5-7 May 2020 (3 days) Time of day: 9:00-17:00 CEST Language: English Place: Live Online (see below) Registration fee: EUR 1850 +VAT Course responsible: Espen... Read More
Advanced VHDL Verification – Made simple, Berlin Germany 5-7 May 2020 (Moved to Live Online)
Advanced VHDL Verification – Made simple. NOTE: This course is now changed to a Live Online course due to the current pandemic: Date: 5-7 May 2020 (3 days) Time of day: 9:00-16:30/17:00 (TBD)... Read More
Advanced VHDL Verification – Made simple, Munich Germany 24-26. November. 2020
Advanced VHDL Verification – Made simple. Date: November 24-26, 2020 (3 days) Time of day: 9:00-16:30/17:00 (TBD) Language: English Place: Munich, Germany Registration fee: EUR 1850 +VAT Course responsible: Espen Tallaksen, Bitvis... Read More