FEATURED PROJECTS
Accelerating FPGA Design (TBD, Germany) 20-21. November 2019
Date: November 20-21, 2019 (2 days) Time of day: 9:00-16:30/17:00 (TBD) Language: English Place: TBD, Germany Registration fee: EUR 1250 +VAT, Course responsible: Espen Tallaksen, Bitvis AS (Mobile: +47 934 21 277)... Read More
Advanced VHDL Verification – Made simple (Stuttgart), Germany) 12-14. November. 2019
Advanced VHDL Verification – Made simple. Date: November 12-14, 2019 (3 days) Time of day: 9:00-16:30/17:00 (TBD) Language: English Place: Stuttgart, Germany Registration fee: EUR 1850 +VAT Course responsible: Espen Tallaksen, Bitvis... Read More
Advanced VHDL Verification – Made simple (Copenhagen, Denmark) 18-20. June. 2019
Advanced VHDL Verification – Made simple. Date: June 18-20, 2019 (3 days) Time of day: 9:00-16:30/17:00 (TBD) Language: English Place: Copenhagen, Denmark(at Circle Consult in Nærum, Rundforbivej 271A) Registration fee: EUR 1850... Read More
Advanced VHDL Verification – Made simple (Oslo, Norway) 13. Nov. 2018
Advanced VHDL Verification – Made simple. Date: November 13-15, 2018 (3 days) Time of day: 9:00-16:30/17:00 Language: English Place: Scandic Hotel Asker Asker (just outside Oslo), Norway Registration fee: NOK 19.000 (for multiple participants... Read More
Advanced VHDL Verification – Made simple (Ankara, Turkey) TBD. Nov. 2018
Advanced VHDL Verification – Made simple. Date: November TBD, 2018 (3 days) Time of day: 9:00-16:30/17:00 Language: English Place: Ankara, Turkey Registration fee: TBD Course responsible: Espen Tallaksen, Bitvis AS (Mobile: +47... Read More
Advanced VHDL Verification – Made simple (Stockholm, Sweden) 2. Oct. 2018
Advanced VHDL Verification – Made simple. Date: October 2-4, 2018 (3 days) Time of day: 9:00-16:30/17:00 Language: English Place: Stockhom, Sweden Registration fee: SEK 19.000 (for multiple participants from the same company: 2nd: SEK... Read More