FEATURED PROJECTS
Advanced VHDL Verification – Made simple, * Live Online, 5-7 May 2020 (EMEA/APAC time zones)
Advanced VHDL Verification – Made simple. Date: 5-7 May 2020 (3 days) Time of day: 9:00-17:00 CEST Language: English Place: Live Online (see below) Registration fee: EUR 1850 +VAT Course responsible: Espen... Read More
Advanced VHDL Verification – Made simple. – – – Course On Request
Public or On-site course on request Advanced VHDL Verification – Made simple. Date: TBD Time of day: 9:00-16:30/17:00 (TBD) Language: English Place: Public or On-site Course fee: To be agreed Course responsible:... Read More
Advanced VHDL Verification – Made simple, Berlin Germany 5-7 May 2020 (Moved to Live Online)
Advanced VHDL Verification – Made simple. NOTE: This course is now changed to a Live Online course due to the current pandemic: Date: 5-7 May 2020 (3 days) Time of day: 9:00-16:30/17:00 (TBD)... Read More
Advanced VHDL Verification – Made simple, Munich Germany 24-26. November. 2020
Advanced VHDL Verification – Made simple. Date: November 24-26, 2020 (3 days) Time of day: 9:00-16:30/17:00 (TBD) Language: English Place: Munich, Germany Registration fee: EUR 1850 +VAT Course responsible: Espen Tallaksen, Bitvis... Read More
Advanced VHDL Verification – Made simple (Oslo, Norway) 20-22 Nov. 2019
Advanced VHDL Verification – Made simple. A general introduction to modern verification methodology and to UVVM – as the fastest growing FPGA and ASIC verification methodology in Europe. (26% of all FPGA designers... Read More
Advanced VHDL Verification – Made simple (Stuttgart), Germany) 12-14. November. 2019
Advanced VHDL Verification – Made simple. Date: November 12-14, 2019 (3 days) Time of day: 9:00-16:30/17:00 (TBD) Language: English Place: Stuttgart, Germany Registration fee: EUR 1850 +VAT Course responsible: Espen Tallaksen, Bitvis... Read More