All courses may be held as
- on-site (as is or adapted) on request; or
- as an open course every time sufficient demand has accumulated
Accelerating FPGA VHDL Verfication
This course a based on the verification part of 'FPGA Development Best Practices' below, but extended with more subjects, details and lots of labs.
On average half the development time for an FPGA is spent on verification.
It is possible to significantly reduce this time, and major reductions can be accomplished with just minor adjustments. It is all about Overview, Readability, Maintainability and Reuse at all levels – and you achieve all of this with the right methodology and a good structured architecture.
- Making a simple VHDL test bench step-by-step
- Using procedures and making good BFMs
- Applying logs, alerts, value and stability checkers, awaits, etc...
- Making an advanced VHDL test bench step-by-step
- Assertions, randomisation, constrained random, coverage, debuggers, monitors
- Verification components and testbench architecture for advanced Verification
- Verification reuse and preparations for reuse
- Making testbenches as simple as possible – adapting to the DUT complexity
- Structuring, Debugging, Overview, Maintainability, Extendibility
- Examples and labs using UVVM
These issues are the main subjects of this course
See one course example here: /events/accel-fpga-verifi,-berlin-2016/
Accelerating FPGA and Digital ASIC Design
This course a based on the design part of 'FPGA Development Best Practices' below, but extended with more subjects and details.
Digital design for FPGAs and ASICs has a huge improvement potential with respect to development time and product quality.
A lot of time is wasted on inefficient design and lack of awareness and knowledge of the most critical digital design issues. This also seriously affects the quality of the end product. The really good thing is that this huge improvement potential can be realised just by making a few important changes to the way we design.
The most important design related issues to improve are:
- Design Architecture & Structure
- Clock Domain Crossing
- Coding and General Digital Design
- Reuse and Design for Reuse
- Timing Closure
- Quality Assurance - at the right level
These issues are the main subjects of this course
See one course example here: /events/accel-fpgaasic-design,-berlin-2016/.
FPGA Development Best Practices
This well established course (previously from Digitas) has been held in DK, SE and NO several times – with very good feedback from the participants (from both really experienced and less experienced designers). Presenter is Espen Tallaksen, – as when this course was previously arranged by Digitas and Data Respons.
This course is packed with relevant and pragmatic Best Practices for FPGA development. It is complementary to the courses for tools, technologies, design/verification languages and digital design from Altera, Xilinx, Aldec, Mentor, Esperan, Doulos, etc. They all have excellent courses for their targets, but our 'FPGA Development Best Practices' course is unique in its focus on design practices for better quality products and more efficient projects.
Our presentation from FPGAworld and FPGA-forum on 'Bugs and Problems - Worst disasters' (now called 'Backgrounder for....') gives a good introduction to why some Best Practices are in deed very important for quality and efficiency.
Please also see this additional information about the course.
See also the result of the written feedback (evaluation form) from our course in Stockholm Nov. 19-20, 2014, with 15 participants from Sweden, Denmark and Norway.
Note that a 3-day version is also possible. This would have additional presentations on design, coding and quality issues.
The total course has the following approximate split on main subjects
- 35% Design – architecture, structure, issues, coding
(Mainly language independent, but examples are shown for VHDL)
Please send us an email if this course could be of interest to you or your company.
FPGA Product Quality and Development Efficiency - For Technical Managers
This course is targeted at Technical managers, Project managers and and other decision makers who are involved in making electronic (embedded) systems with one or more FPGAs.
Important aspects covered in this course are:
FPGA Design Best Practices
This course is based on 'FPGA Development Best Practices', but with focus on design issues only.
FPGA Verification Best Practices
This 1-day course is based on 'FPGA Development Best Practices', but with focus on verification issues only.
FPGA VHDL Conventions
This is a half day course on writing better VHDL using proper conventions. The focus in this course is to explain the reason for the conventions and why they help improving quality and efficiency.
FPGA Quality Assurance for developers
This is a half day course on the most important aspects of FPGA development with respect to quality improvement. Some important issues are methodology coordination, checklists and reviews, but also touches on architecture and coding.
It is possible to combine the courses as you wish for a targeted on site course.