VHDL simulation transcript is important for quality and efficiency

  

  • Sometimes you want to see what has actually happened in a simulation
  • Sometimes you want to see whether you have covered all functional aspects of your design
  • Sometimes you want to see the various accesses made on your interfaces
  • Sometimes you want to see what happened just before something failed – to debug a problem.

There are so many reasons for making your testbench produce more information on activity, success, problems, bugs, protocol details, etc, - but still - most testbenches produce far too little progress information. Some major reasons for this are bad habits (due perhaps to low awareness of improvement potentials), lack of time (but losing far more time at a later stage), inadequate testbench support (to efficiently make good progress reports) and the absence of a good testbench methodology.

All of this has a very good, very simple, and no-cost solution. Bitvis Utility Library is a free, open source VHDL library that will yield a major efficiency and quality improvement for almost all FPGA (or ASIC) development. The library has been downloaded all over the world, and the feedback has been very good – also from specialists in the VHDL community.

Probably the best feature of this library is that it has an extremely low user threshold, and at the same time has advanced options available when needed for more complex testbenches. You will be up and running, making far better testbenches in less than one hour. 
Invest 10 minutes to browse through our powerpoint presentations on ‘Making a simple, structured and efficient VHDL testbench – Step-by-step'  and/or  ‘Bitvis Utility Library Concepts and usage’, - both available for download (with no registration). The library may be downloaded from the same page. 

If this looks interesting you could also watch the webinar we made for Aldec to get more details. 
The library is free, and there is no catch.   Enjoy  :-)

 

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