UVM (and SystemVerilog) are new buzzwords within advanced ASIC verification, but are often mentioned also for FPGA verification. There is no doubt that verification is a major and increasing challenge for FPGA development, but for most FPGA projects UVM is definitely not the answer to this challenge. For almost all companies using VHDL for their FPGA development it doesn’t make sense to change to UVM/SystemVerilog for verification. In fact, in most cases changing to UVM/SystemVerilog will result in lower efficiency and a higher cost. UVM/SystemVerilog is a huge step in complexity, a totally different way of thinking, a new language and methodology – very different from VHDL and component orientation, and also a very expensive path with respect to tool cost.
However, UVM and SystemVerilog (and SystemC) have introduced (or standardised) some very interesting concepts which in themselves definitely may improve lots of verification scenarios. Most of these concepts are language independent and possible to implement in VHDL. Thus it would make very much sense to introduce these concepts into our VHDL based testbenches, - as evolutionary and logical steps for the designers, allowing them to continue with their current language and component orientation and then take a small step further whenever needed.
The main problem with this approach so far has been that designers have built ad-hoc solutions, not sufficiently structured, with insufficient focus on understandability, maintenance and re-use. Over the last few years this has been changing.
With these improvements VHDL has already taken significant steps as a verification language and methodology. Now Bitvis introduces UVVM (Universal VHDL Verification Methodology) to take another major step. In the first release of UVVM we have focused on the main and most important missing methodology aspect - VHDL Verification Components (VVC).
Most FPGAs and modules have two or more interfaces that need to operate simultaneously, and lots of corner cases arise from the access to these interfaces at arbitrary times. Even a simple module like a UART has lots of corner cases - for instance due to the possibility of CPU reads of the RX-register being executed at random times with respect to data actually entering the RX register/FIFO/buffer from the RX interface. To verify that all these corner cases are OK requires simultaneous stimuli (and monitoring) of all interfaces and the ability to skew these accesses with respect to each other. In most TBs this is handled in a very unstructured, ad-hoc manner.
UVVM provides a simple, structured and reusable approach to this problem. In UVVM we have taken care of all the complexity of distributing commands to VVCs, queuing them inside the VVCs and executing them towards the DUT. The VVCs may also have local sequencers, controlled by the main/central TB sequencer, and of course a system to synchronize the various VVCs so that the central sequencer is easy to understand, extend and maintain. UVVM also provides an excellent reporting system using the verbosity control of Bitvis Utility Library, allowing the user to follow a command on its way from the sequencer to actual execution. Most of all, UVVM offers a methodology and usage that is easy to understand for anyone with a VHDL or software background. UVVM also allows random stimuli in a controlled manner.
UVVM will be released in Q2 2015, but with beta-release for selected customers Q1 (2015).
This is only the first stage. We have several enhancements in mind for future releases. These will all be published on our website.
An introduction to UVVM will be presented at FPGA-forum in Trondheim, February 12, 2015. The presentation will be made available on our web-site in February.