A free library for good testbench checking functionality

TB Purpose

The purpose of a testbench (TB) is to check the behaviour of your DUT (Device Under Test). This really goes without saying, - but sometimes stating the obvious is really needed. For any testbench you always provide stimuli and check the response. Sometimes this is a simple operation, and sometimes this is really complex. Most testbenches do however have some basic checking aspects in common.

Basic Checking Aspects

  • Checking a signal value against an expected value – sometimes with partial don’t care or a margin
  • Checking stability on a given signal (that a certain time has elapsed since the last signal event)
  • Waiting for a signal change or specific value on a signal

Improving TB development efficiency and quality

The checks above are easily implemented in VHDL, or better - in self-made sub-programs. The challenge is not to make the actual procedures and functions, but to add functionality to these checks to allow far more efficient TB development and problem debugging. The following are some examples that will significantly speed up your FPGA development:

  • Reporting the actual mismatch - like ‘was 0xFE, but expected 0xFF’ yields important debug-information
  • Reporting what is actually being checked – like ‘Checking correct CRC for packet 1’ yields another piece of important information
  • Reporting the source of a failing mismatch leads the problem search in the right direction (e.g. problem in UART 1)
  • A positive acknowledge when passing the test is very useful when building the TB, BFMs, Analysers, etc
  • Allowing the positive acknowledge to be filtered away is really useful when this part is working
  • Counting alerts (errors, warnings, etc) and potentially stopping on N errors allows good debugging flexibility
  • Ignoring certain alerts is useful when provoking a misbehaviour
  • Timeout on waiting for an event to happen inside a given time window – with a proper message – rather than hanging on a ‘wait until’

Adding this functionality makes everything simpler, faster and better. The TB code will be more understandable (by anyone) and far simpler to maintain and extend. Debugging of both the DUT and TB will be far more efficient. The progress report will be more understandable and make more sense to anyone. And the quality of the design and the TB will increase significantly.

A major impact on TB development

Now going back to the introduction. The sad fact is that for most testbenches a lot of development time is wasted and the quality of the TB is insufficient, and a major reason for this is the lack of a structured approach to logging and checking. The good news is that all this functionality is available for free through Bitvis Utility Library. Bitvis Utility Library is a free, open source VHDL library that will yield a major efficiency and quality improvement for almost all FPGA (or ASIC) development. The library has been downloaded by developers all over the world, and the feedback has been very good – also from specialists in the VHDL community.

Bitvis Utility Library also has excellent support for logging/reporting and verbosity control (see a previous post on LinkedIn). The combination of the logging/reporting/verbosity and checking support - all provided with Bitvis Utility Library – now makes it possible to develop more structured testbenches, with better verification of DUT functionality and better simulation transcripts with progress report and debug-support – and at the same time reduce the development workload and schedule.

For more advanced testbenches you might need additional support and TB structure for coverage (e.g. via OSVVM) and simultaneous access (stimuli/check) (e.g. via UVVM) on multiple interfaces, but you still need the functionality provided by Bitvis Utility Library as your base.

A very low user threshold

An essential feature of this library is that it has an extremely low user threshold, and at the same time has advanced options available when needed for more complex testbenches. You will be up and running, making far better testbenches in less than one hour.

Invest 10 minutes to browse through our powerpoint presentations on ‘Making a simple, structured and efficient VHDL testbench – Step-by-step' and/or ‘Bitvis Utility Library Concepts and usage’, both available for download (with no registration) from /resources/utility-library-download/. The library may be downloaded from the same page.

If this looks interesting you could also watch the webinar we made for Aldec to get more details.

The library is free, and there is no catch. Enjoy :-)