Presentations & Articles

Note that some presentations are PDFs of PowerPoint with dynamic animation. This means that some layers of text or images may be hidden behind others, and of course that animation is no longer available.

Please get in touch if you would like us to present specific presentations - or if you would like to attend one of our Best Practices courses.

Table of contents:

 

The critically missing VHDL testbench feature - Finally a structured approach
(@FPGAworld, Stockholm, 8 Sept 2015)

Verification is 51% of total FPGA development time (cf 'Functional Verification Study' from Wilson Research Group). Even more for control or protocol oriented design.
Ignore this and you will iterate forever in the lab and suffer from bad product quality. The root cause is corner cases triggered by certain input and FSM combinations. Hitting a given corner case in normal simulation is very unlikely, - but in the final product it will hit you hard. A structured VHDL approach to verifying such corner cases has not been commonly available. UVVM (Universal VHDL Verif. Meth.) changes this picture completely..

FPGAs - a 1000x performance increase. How? What? Why?
(@NDC, Oslo, 18 June)

An FPGA is programmable hardware and yields an extreme performance for time critical operations. Throughput and latency are magnitudes better than software solutions due to the massive parallelism of real hardware. FPGAs are basically the best of both worlds; the speed of hardware and the flexibility of software. This presentation will show you the basics of FPGA’s - the technology, the functionality, the methodology, the opportunities - and some limitations.

The video from the NDC presentation is now available.

Linux – Not real-time!(pdf)

"it may sound disappointing, but the Linux operating system is not an RTOS. This article focus on some aspects of interrupt handling in Linux kernel related to real-time performance.

A free library for good testbench checking functionality 

The purpose of a testbench (TB) is to check the behaviour of your DUT (Device Under Test). This really goes without saying, - but sometimes stating the obvious is really needed.  
For any testbench you always provide stimuli and check the response. Sometimes this is a simple operation and sometimes this is really complex. Most testbenches do however have some basic checking aspects in common.

Introduction to generic programming (pdf)

Generic programming is about writing your code portable, modular and easily maintainable. There are however limits for how much effort you want to put into making your code generic. This article will give an overview of different levels of genericity as well as some guidelines to follow.

"UVM for VHDL" - UVVM: Universal VHDL Verification Methodology

Complex designs often need advanced testbenches. SystemVerilog and UVM are being pushed as "the solution", but VHDL and selected libraries is most often a far better solution.

VHDL simulation transcript is important for quality and efficiency

The structure of your testbench is important, but so is definitely also the progress information being produced by that testbench.

Virtual Machines for Embedded software development (pdf)

Using a virtual machine (VM) as a development platform for embedded software has many advantages. VMs enable better portability, greater redundancy, lower setup- and recovery times. The ability to archive the entire development environment allows better control over software packages and libraries needed for a specific project. Furthermore, you have the added benefit over having the ability to hand over the whole development environment to the customer after project completion in addition to the developed source code. The VMs host machine will need to have more memory than a machine that would run without a VM. When using a VM for development it is important to have a clear strategy in how licensing and source control should be handled.

The Good, the Bad and the Ugly (pdf)

(Presented at FPGA-forum)
The way you implement your FPGA design and write your code has a huge impact on your development efficiency and product quality. The strange thing is that even many experienced designers tend to write both bad and ugly code. Does it matter if the code is ugly if it works in the lab? Yes – definitely, and for several reasons. First of all – the probability that ugly code has serious bugs is far higher than for good code. Also any change made to ugly code has a far higher risk of introducing bugs. And of course – ugly code makes it far more difficult to do a proper review. More time consuming, often frustrating, and with a far worse review quality. Bad and ugly code often results in errors that may be difficult to find and terrible to correct. This presentation will show some examples of bad and ugly code, how they result in inefficiency or bugs, and also suggest some remedies and suggestions for improvements – in order to write good code. (Examples will be in VHDL, but apply equally well for other languages)

Methodology Coordination, - Is it really needed? (pdf)

(Presented at FPGA-forum)
Most companies have a strong focus on coordinating company critical processes, like sales, marketing, accountancy, department management, QA, etc. Lots of companies have also understood that project management is equally critical, but why is the development methodology treated so differently? Why do so many companies focus so little on coordinating their development methodology, - and what is the consequence of that?

Achieving the right FPGA design quality – Could reviews save the day? (pdf)

(Presented at FPGA-forum)
Some of the most important quality aspects of an FPGA are:
a) Functional quality. Does the FPGA perform its intended tasks - for all corner cases – and with no hiccups?
b) Ease of modification. How easy is it to modify the design or add functionality – during or after the initial design?
c) Readability and understandability. How easy is it (especially for somebody else) to understand the design – e.g. for a handover Proper functional verification may help you a long way with the “soft” part of the functional quality, but not with the hardware-related issues like timing and clocking. Lint-tools may help detect some bad coding style and check coding conventions, but this is a very minor part of designing for modification, readability and understandability.
Thus in order to achieve the right quality we need good walk-throughs and reviews.
Unfortunately however, most reviews are close to useless.
This presentation exemplifies some critical quality aspects and suggests solutions on how to handle these.

Improve your VHDL testbench - A practical approach (pdf)

(Presented at FPGAworld)
Most simple testbenches have close to no structure, are terrible to modify and hopeless to understand. They often take far too much time to implement, and provide close to no support when debugging potential problems. A general solution to this problem was presented here by Digitas in 2009, and by Bitvis as an Aldec webinar in April 2013. (Please see bitvis.no/downloads) Bitvis Utility Library is now available as open source to support this solution. This allows a major improvement for most companies. This presentation goes beyond the webinar and presents the features, concept and usage of the library.

Developing an FPGA module with a strong focus on efficiency, quality and modifiability (pdf)

(Presented at FPGA-forum)
Many designers and project managers consider efficiency on one hand and quality and modifiability on the other hand to be inverse proportional. In other words improving the quality/modifiability has an efficiency penalty, and improving the efficiency results in lowering the quality. In most cases unfortunately - they are right. However, by properly structuring your module development you can in fact increase your efficiency while at the same time improving the quality and modifiability. It's all a question of methodology, implementation coordination and approach.
This presentation will give a brief overview of some of the most important issues to consider - and show an example on how this could be applied to a real module design.

FPGA-verifikasjon: En kick-start plattform (Norw. only) (Elektronikk 13-03)

God verifikasjon er kritisk for kvaliteten på en FPGA og dermed også sluttproduktet. Strukturert verifikasjon er kritisk for tidsbruken, men også som et grunnlag for god verifikasjon og debugging. Det første som må på plass er en grunnleggende infrastruktur som tilbyr funksjonalitet man alltid trenger – for enhver testbenk. Bitvis legger nå ut en slik infrastruktur – i form av et VHDL-bibliotek - til gratis bruk for alle.

FPGA-utvikling: Full fart, men lite styring (Norw. only) (Elektronikk 12-08)

FPGA-utvikling kunne gått 20-50% raskere, med lavere risiko og bedre kvalitet – med null eksterne investeringer. Hva gjøres galt - og hvordan kan vi ta ut dette potensialet?