UVVM - Overview

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UVVM: Universal VHDL Verification Methodology

UVVM is a VHDL Infrastructure, System, Framework and Methodology for making better VHDL testbenches. 

 

UVVM is a family of VHDL Verification support products.  What is UVVM? 

There are additional support libraries/components - like BFMs (Bus Functional Models) and VVCs (VHDL Verification Components). Some free and Open Source components are included in the UVVM VVC framework download file (ZIP).
Quick-References are available for all BFMs and VVCs.

So far the following family members are available:

 

Typical configuration

This example is illustrating a typical and very simple testbench. A centralized test sequencer interfaces the DUT via all the attached VVCs.

All communication commands are available through the BFM and VVC packages.

 

 

 

  

UVVM Framework Storm