UVVM is a complete VHDL verification environment with the following features:
- Component oriented using VVCs (VHDL Verification Components)
Allows a very good overview and a Lego-like assembly.
- Transaction based (TLM)
May distribute commands from a central sequencer to VVCs in a very simple and understandable manner - for autonomous execution of the commands by the VVCs towards the DUT.
- Provides a handshake mechanism for VVC communication that allows excellent debugging.
The mechanism is hidden from the user who only sees straight forward BFM-like procedures.
- Verbosity control and command tracking
- Supports Constrained Random stimuli
(From central sequencer, or locally in the VVC)
- Supports Functional Coverage
- Reporting and Coverage driven test cases
- Central AND Local Sequencer control
- Completion control
- Drivers, Checkers and Monitors
- Scoreboard system
- Allows user definable error injection
UVVM will be implemented in steps. First priority is a testbench structure with VVCs and distribution of commands, as this promotes an excellent verification structure and a good means for finding and debugging specification and implementation related corner cases.
Key philosophy and characteristics of UVVM are:
- Simplicity and Abstraction
Often a difficult combination, but the component and procedure oriented system provides users with full control and overview of their test cases
An easily extendible system that allows any user to very efficiently make their own VVCs and functionality extensions
- Efficient reuse
- Major reuse from one VVC to another
- Direct reuse of VVCs between module and top level testbenches
- Overview, Readability and Maintainability
Major improvement due to the structured testbench approach
- Simplifies Concurrent Design and Verification
(For all of the above reasons)
UVVM will be presented at FPGAworld in Stockholm September 8th 2015, and will be released soon after that on our web site.