UVVM Utility Library

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Universal VHDL Verification Methodology (UVVM) - Utility Library

Open source VHDL testbench (TB) infrastructure library for verification of FPGA and ASIC. 

Yields a platform with functionality for logging, alert handling, checkers, awaits, random and some string handling support.

 

Bitvis Utility Library is an open source VHDL testbench (TB) infrastructure library for verification of FPGA and ASIC. It should work with any VHDL simulator.

The library provides a verbosity control system and a structured logging mechanism for making a good simulation record. It also provides an alert handling system and lots of basic methods to check your simulation progress.

The key benefits of using this library are:

  • Simpler and faster testbench development
  • Significantly less code per test case
  • Far more readable and modifiable test cases
  • A more uniform test sequencer coding style
  • A good simulation progress and result report
  • An excellent log for debugging DUT and TB

 

UVVM Utility Library

Version v2.0  (2017-02-14)

Open source.  MIT license.
(Download includes optional OSVVM: 
under Artistic License 2.0)

May be downloaded directly from GitHub or via the Github zip-file generator

   

'Making a simple, structured and efficient VHDL testbench – Step-by-step' 

Presentation on how to implement a good basic testbench independent of 3. party libraries, but using Bitvis Utility Library as an examle.
(UVVM Utility Library is the successor of Bitvis Utility Library)

Note: The video is a Webinar made for Aldec. You need to register there to see it.

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'UVVM Utility Library Concepts and usage' 

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