FPGAworld Conference 2017, Stockholm 19. Sept, Copenhagen 21. September
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FPGAworld 2017 in Stockholm Sept. 19, Copenhagen Sept. 21. Bitvis will give a presentation in the industrial track: Constrained Random and Functional Coverage for VHDL testbenches – controlled in a structured manner by Espen Tallaksen Full Program for Stockholm Full … Read More

Auto generating code and generic FPGA register access from software 16. Feb. 2017
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Software and FPGA developers often struggle with synchronization of the register map. Parallel register access from multiple software applications is also a difficult issue to deal with. Auto generation of code from a single source keeps the register map synchronized. … Read More

FPGAworld 2016 13.Sep.2016
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FPGAworld 2016 in Stockholm Sept. 13 Bitvis will give a presentation in the industrial track in Stockholm: Verifying corner cases in a structured manner – using VHDL Verification Components (VVC) UVVM provides overview, readability, maintainability and reuse for medium to … Read More

3x UVVM at FPGA-Kongress in Munich 14-16 July 2016
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is one of the largest FPGA conferences in the world. We are really proud that two presentations and a tutorial have been accepted, and this only 5 months after releasing UVVM VVC Framework  🙂 Bitvis will have two presentations and … Read More

UVVM Presentation++ in Bergen 28. September 2015
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The following presentations will be given in Bergen Monday Sept. 28, 2015. (at Bergen University College). In the morning – a Guest lecture – primarily for students at University of Bergen and Bergen University College, but also open for FPGA … Read More

FPGAworld Sept. 2015
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Bitvis is again giving technical presentations at FPGAworld (2015) – in Stockholm Sept. 8 – in Copehagen Sept. 10   ——- Bitvis will give the following presentation in the industrial track: ‘The critically missing VHDL testbench feature – Finally a … Read More

The critically missing VHDL testbench feature – Finally a structured approach (@FPGAworld, Stockholm, 8 Sept 2015)
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Verification is 51% of total FPGA development time (cf ‘Functional Verification Study’ from Wilson Research Group). Even more for control or protocol oriented design. Ignore this and you will iterate forever in the lab and suffer from bad product quality. … Read More

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