UVVM: "UVM for VHDL"

Published: 22.Aug.2014

Universal VHDL Verification Methodology (UVVM)

Step 1: How to handle verification of FPGAs and modules with two or more simultaneously active interfaces – to detect the hard to reach corner cases.

Will be presented at FPGAworld in Stockholm, Sept. 9, 2014 (track C6)
Abstract is available there.