Bitvis has perhaps the best SystemVerilog experience available in Norway, with lots of knowledge also on UVM and VMM. This experience and knowledge has been acquired through working on a very complex state-of-the-art data communication ASIC over the last few years. Three of our designers have played major roles in – to our knowledge - the most advanced verification project ever in Norway. The verification environment was utilising SystemVerilog to its full extent, and our designers were in the driving seat when defining and developing this testbench and testcases.
So why haven’t we pushed this methodology more at FPGA-forum and towards our customers?
The simple reason for this is that we know that SystemVerilog is an excellent solution for ASIC developers and FPGA-developers using Verilog as their implementation language, but SystemVerilog is not a good solution for FPGA-designers using VHDL as their implementation language. For these designers VHDL is clearly the best, most efficient and lowest cost verification language, and Bitvis is committed to further improve the VHDL advantage for this group, by providing Bitvis Utility Library for free, and very soon release our UVVM methodology and library that together with OSVVM will make VHDL an even better alternative. Thus allowing a simple, but important evolution on VHDL verification methodology. An evolution that makes sure VHDL stays the far better alternative for 99% of FPGA designers in Norway.
However, we do of course offer our top SystemVerilog competence when that is considered the best solution for our customer. So currently we are working for a new customer helping them implement their ASIC and SystemVerilog/UVM testbench.
We don’t want to push any language preferences on our customers, but due to our leading expertise in both verification languages we are able to advise our customers - and even more important – make structured and efficient, re-usable and easily maintainable testbenches based on the best from both worlds.