An SPI VHDL verification component (VVC) is now available for free with UVVM - the Universal VHDL Verification Methodology (open source).
The SPI VVC may be uconfigured as a master or a slave, and it may be used as a BFM (Bus Functional Model: Pure SPI interface access procedures) or as a VVC (to be interfaced directly to the SPI interface and allowing queuing of commands and simultaneous or skewed access in a controlled manner).
UVVM is free and open source, and is a game changer for VHDL testbences when it comes to Overview, Readability, Maintainability, Extendibility and Reuse. Please see 'Advanced VHDL Verification - Made simple - For anyone' for a brief introduction to the major benefits of UVVM.
The following free and open source VIPs are now available as BFMs and VVCs :