There is a huge interest for UVVM (Universal VHDL Verification Methodology).
We are now presenting UVVM at even more conferences around Europe.
Tuesday October 11 we will present\
'A game changer for VHDL verification:
- Advanced VHDL Verification
- Made simple - For anyone'
at NMI FPGA Network 'Design tools and Methodologies' in Swindon (UK)
Wendesday October 19 we will present a tutorial (90 minutes) on the same subject, but going deeper into the material.
'UVVM - A game changer for FPGA VHDL Verification'
at DVCon-Europe in Munich (DE)