Presenting UVVM at FPGAworld 2015

Published: 10.Aug.2015

Bitvis is again giving technical presentations at FPGAworld (2015)

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Bitvis will give the following presentation in the industrial track:

'The critically missing VHDL testbench feature - Finally a structured approach'

Verification is 51% of total FPGA development time (cf 'Functional Verification Study' from Wilson Research Group). Even more for control or protocol oriented design.
Ignore this and you will iterate forever in the lab and suffer from bad product quality. The root cause is corner cases triggered by certain input and FSM combinations. Hitting a given corner case in normal simulation is very unlikely, - but in the final product it will hit you hard. A structured VHDL approach to verifying such corner cases has not been commonly available. UVVM (Universal VHDL Verif. Meth.) changes this picture completely.

Over the last few years VHDL 2008 and libraries like Bitvis Utility Library (BVUL), OVL and OSVVM has speeded up VHDL testbench development significantly, and at the same time allowed a major quality improvement.
So far however, there has been no proper support for handling the actual testbench structure when controlling multiple interfaces.  For multiple simultaneously active interfaces, this could be really critical when it comes to verify cycle related corner cases. Even a simple UART may have several such hard to verify corner cases, and in most projects they are not verified or tested at all - resulting in a product that may have serious corner case bugs. And this even for a simple UART....
There are libraries available that do support control of simultaneously active interfaces, but they are either rather unstructured, very complicated to use or difficult to maintain. Due to their synchronization mechanisms they also make it really hard to get a proper overview of the testbench and test cases.

This presentation will show a typical corner case bug, the typical approaches to finding such bugs, and a structured approach to increase productivity. This includes coding efficiency, potential reuse, overview, readability, extendability, maintainability, debug-friendliness and a lowest possible user threshold.

UVVM is not only about testbench structure. It also provides great progress information at all levels and it allows both directed tests and constrained random and coverage based testbenches.

 

Bitvis will give the following 1,5 hour tutorial after lunch - as a follow-up on the presentation above - allowing a better understanding of the general needs and what UVVM provides.

The tutorial is free, but requires registration (only possible in the reception at FPGAworld in Stockholm on the same day). Seating is limited.

Universal VHDL Verification Methodology (UVVM)

This presentation will explain how UVVM may help you reduce your verification time significantly - and at the same time improve your product quality.
Corner cases in the specification and your implementation often result in lots of FPGA bugs. Most of these bugs are very difficult to detect in normal simulation or lab test, and very often quite a few of these bugs are not detected until experienced by the customer.
UVVM is a complete VHDL based verification environment platform that will cover all the most important aspects of FPGA verification. We will show how this works and how you can use this platform to make your own testbench and your own structured verification components based on the examples provided. As a simple example it took only one single hour to make a UART verification component from scratch (but based on a simple bus interface verification component and UART BFMs.  This new UART verification component could then be used in a very structured and reusable 
verification environment.
Please note that this presentation assumes that you have attended the presentation 'The critically missing VHDL testbench feature - Finally a structured approach' in track A4 earlier today.
UVVM will be released very soon after FPGAworld.