Bitvis is giving two times two guest lectures.
First at Bergen University College and Univerity of Bergen (combined) Oct. 30, and then University of Oslo Nov. 6 2013.
The two lectures are:
a) Bugs and problems - Worst disasters
b) Making a simple testbench - step-by-step
As a consultant you see lots of different projects in many companies; - sometimes as a designer, sometimes as a coordinator and sometimes just helping out with implementation, verification, debug or review. This presentation will give an overview of the worst project and product consequences with respect to both bugs and delays. The worst sources of these bugs and delays will be presented, and some general remedies are proposed
Main focus on product quality and development efficiency.
Abstract b, Bergen)
Most simple testbenches have close to no structure, are terrible to modify and hopeless to understand. On top of that they take far too much time to implement and provide close to no support when debugging potential problems.
This presentation will show and exemplify how to build a far better testbench with respect to all these issues - in significantly less time. The presentation will also explain how this verification approach even results in reduced design time and reduced debug time.
Bitvis Utility Library is open source and should really be used by anyone making a VHDL testbench (unless they have a better system available). The library was released in April 2013 and is already being used by several Norwegian companies.