Bitvis is giving a guest lecture at Bergen University College and University of Bergen (combined) Nov. 5
- and a Presentation at Bergen FPGA Competence group
At Bergen University College and University of Bergen
Making a simple testbench - step-by-step
Most simple testbenches have close to no structure, are terrible to modify and hopeless to understand. On top of that they take far too much time to implement and provide close to no support when debugging potential problems.
This presentation will show and exemplify how to build a far better testbench with respect to all these issues - in significantly less time. The presentation will also explain how this verification approach even results in reduced design time and reduced debug time.
Bitvis Utility Library is open source and should really be used by anyone making a VHDL testbench (unless they have a better system available). The library was released in April 2013 and is already being used by several Norwegian companies.
(Bitvis Utiility Library is being used there already as a part of the study)
At Bergen FPGA Competence group
1) Bugs and problems – Worst disasters
As a consultant we see lots of different projects in many companies; - sometimes as a designer, sometimes as a coordinator and sometimes just helping out with implementation, verification, debug or review. This presentation will give an overview of the worst project and product consequences with respect to both bugs and delays. The worst sources of these bugs and delays will be presented, and some general remedies are proposed.
(An extended version of this presentation - just used as keynote at ABB Embedded Systems Forum)
2) Brief info on Bitvis Utility Library, OSVVM, UVVM