Bitvis Utility Library, a free and open source verification library for FPGA development Is receiving very positive feedback – now also from outside Norway. In ‘It’s no accident that Aldec offers the best VHDL-2008 support’ Bitvis is mentioned both in the article itself and “Related Resources” through our webinar “Making a Simple, Structured and Efficient VHDL Testbench”. The webinar shows how to verify an FPGA and how Bitvis Utility Library supports this.
It is also great to see that the same webinar from Bitvis is now also mentioned on ‘Semiwiki’.
The library itself has been downloaded more than 500 times, which is really impressing in the FPGA community. There seems to be a great interest in particular from the US, UK, Sweden and Germany, but also from lots of other countries all around the world like Brazil, China, Indonesia, India and South Africa.
One of the main international gurus on VHDL, Jim Lewis (Chair of the IEEE VHDL standards committee and co-founder of the Open Source VHDL Verification Methodology - OSVVM) has even characterized the library and methodology as ‘sophisticated’ and indicated that this might be the best of its kind. This makes us really proud