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Free VHDL Verification seminar – One time only. 29. April 2015

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Free verification seminar for simple and advanced verification

Our Free & Open source, Bitvis Utility Library (BVUL) was released two years ago accompanied by a free, one time only introduction seminar – with very good attendance. The library is now being used in lots of companies in Norway and in Scandinavia, and it has also gained more and more attention all around the world. Now we introduce UVVM – Universal VHDL Verification Methodology as a level above Bitvis Utility Library to handle more advanced verification challenges.

UVVM is a methodology and verification library that allows a structured approach to verifying modules or FPGAs (or ASIC) with simultaneous activity on two or more interfaces. This is a major challenge in most FPGA projects – very often resulting in unstrucured testbenches, time consuming verification, tedious lab-test iterations or serious bugs popping up at irregular intervals. UVVM can handle this in a structured manner.
UVVM also support Constrained Random and Coverage driven verification.

So once again we arrange a one time only free seminar. This seminar will of course cover UVVM, but as UVVM is building on Bitvis Utility Library we will start the day by going through BVUL. This will allow new BVUL users to get a good introduction to the Bitvis Ulility Library fundamentals and also good verification methodology in general. Existing users may get new ideas on using BVUL more efficienctly and for more complex issues.

After lunch you will get a good overview of UVVM and see why this type of verification approach is critical for making good quality FPGAs in an efficient manner.

 

 

Location: Scandic Hotel Asker
(3 min walk from Asker train station. Asker is 20 min by train from Oslo Central.)

Registration is required.
– Register to info@bitvis.no
– NEW Deadline for registration: April 27th
  BUT – with restricted number of seats.  (36 registered per April 22)
– You may register for any section of the seminar. E.g. for sections ABC or BCDE only
– Registration email must include
– Full name
– Company name
– Email
– Mobile
– List of seminar sections you would like to attend (e.g. ABCDE)
– Note that the number of seats is limited.
– The seminar is free, but there is a no-show fee of NOK 750.

Agenda  – Wednesday April 29th (Preliminary)

9:00 Registration and Coffee
9:30 A Making a simple and structured testbench – step by step.
Including
– Bitvis Utility Library (Free, Open source): Concepts and usage
– Demo
11:00 Coffee
11:15 B Advanced Bitvis Utility Library aspects
How to make good BFMs
12:00 C Lunch
13:00 D Verification of modules or FPGAs (or ASIC) with simultaneous activity on two or more interfaces
– Problem scenario
– A structured solution
– Verification components in general
14:00 Coffee
14:15 E UVVM
– Overview and some critical details
– Usage
– Demo
– More important details
15:45 Questions
16:00 End of seminar

 

Bitvis Utility Library
– Was released April 2013
– F
ree – for anyone – including commercial use
– No restrictrions on use
– Minor restrictions on modifications (typ. license and copyright)
– Open source

UVVM
– To be released in Q2 2015
– A free trial version of UVVM will be available for non-commercial use
– Various pricing models for commercial use
(We will show you the principles on how to make a good verification system,
enabling you to make better testbenches independent of UVVM)

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