FPGA Development Best Practices, Stockholm, Nov. 19-20

Published: 19. Nov 2014

FPGA Development Best Practices     (see flyer)


Date: November 19-20

Time of day: Wednesday 9:00-17:00, Thursday 9:00-16:00

Language: The course will be held in English. All slides are in English

Place: Stockholm, Sveavägen 64 (Realtime Embedded's office)

Registration fee: SEK 10.900  (+VAT)
    (Discount for multiple participants from the same company:
      2nd: SEK 10.000, 3rd: SEK 9.000, 4th: SEK 8.000, 5th: SEK 7.000)    

Lunch and coffee:  Included in the registration fee)

Course responsible: Espen Tallaksen, Bitvis AS     (Mobile: +47 934 21 277)

Registration: By email to Espen.Tallaksen@bitvis.no 

The course will be held in cooperation with Realtime Embedded (Stockholm) for adminstrative issues in Sweden. If you were made aware of this course by Realtime Embedded - please register by email to event@rte.se

There are now sufficient participants to hold the course.
The number of participants is limited. Priorities in order of registration.

A description of the course and related info can be found here  

The feedback from previous course participants in Norway (and Sweden and Denmark) has been very good (from designers at all levels, from 1 to 30 years experience).

Main focus in this course is quality and efficiency improvement, making you a better designer and your company a better product development organisation. The course is very relevant also for digital ASIC development.

In addition to the agenda and information below, please also see the attached presentations for:

a) More information, including scope, target audience, prerequisites, etc
b) Background-information & Motivation. Typical FPGA product and project problems



This is a Best Practices course.
The course is complementary to the courses offered by FPGA vendors and tool vendors - and also complementary to more general courses offered by Doulos, Esperan, etc. and various universities. The broad agenda - with a strong focus on the issues that matter the most for efficiency and quality, makes this a good platform for a pragmatic approach to improving your FPGA projects.
The course is very compact – in order to get the most out of busy designers’ valuable time.

This course may also be held on-site on request - with a duration of one to three days depending on your starting point and level of ambition. Such a course allows some flexibility and adaptation - and would promote more interaction. Presentation in English or Norwegian as requested.

(A description of the course and related info can be found here )