Advanced VHDL Testbenches and Verification (5 days)

Published: 05. May 2014

FirstEDA & Jim Lewis:

Overview
FirstEDA is partnering with SynthWorks to offer our customers access to cutting edge knowledge and insight in the application of VHDL to verification & validation. With all the hype surrounding SystemVerilog (and specifically UVM), the fact that VHDL is intrinsically better suited to this task than Verilog is often overlooked. This 5-day hands-on workshop will provide a unique opportunity to effectively plan your future verification strategy, ensuring that you leverage your existing investment in VHDL tools and knowledge.

Presenter
Jim Lewis has over 28 years of design and teaching experience and is well known within the VHDL community. He is currently the Chair of the VHDL Standards Working Group at IEEE.

Background
During this 5-day course you will learn advanced VHDL coding styles, techniques and methodologies that will ensure you become more productive at design verification and testbenches. All of these techniques are implemented in VHDL. Core topics such as transaction level modelling (TLM), data structures (linked-lists, scoreboards, memories), test generation methods (directed, algorithmic, constrained random, and intelligent testbench), self-checking and functional coverage are explored in depth.

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