Advanced VHDL Verification – Made simple
|Date:||Oct 3-5, 2017 (3 days)|
|Time of day:||9:00-16:30/17:00|
(At Business Centre Winghouse, Oerestads Boulevard 73, 2300 Copenhagen)
|Registration fee:||EUR 1900 (1800 with Promo codes or directly to one of our course partners)
(for multiple participants from the same company as for discounts)
Lunch and coffee: Included in the registration feeNotes:
It is possible to register for day 1 only – if advanced testbenches are not of interest;
– or days 2-3 only – if you already have extensive working knowledge of UVVM Utility Library and methodology – including related BFMs.
Send request to firstname.lastname@example.org
|Course responsible:||Espen Tallaksen, Bitvis AS (Mobile: +47 934 21 277)|
|Registration:||On email to email@example.com or to one of our course partners
Please give the following info: Full name, Company, email, mobile phone, invoice address and any potential invoice reference if needed.
|Deadline for registration:||Sept. 26.
NOTE: Seating is limited, and priority will be given based on time of registration.
A description of the course can be found *** HERE ***