Advanced VHDL Verification - Made simple

Published: 07. Mar 2017

Advanced VHDL Verification - Made simple, , Oslo, Norway, March 7-9

Date: March 7-9, 2017  (3 days)
Time of day:  9:00-16:30
Language:  English
Place:    Oslo (Asker, Scandic Hotel), Norway
(5 minutes walk from Asker train station - on the airport express line)
Registration fee: 

NOK 15.900  (Note: no VAT on courses in Norway)
(for multiple participants from the same company: 2nd: NOK 15.000, 3rd: NOK 14.000, 4th: NOK 13.000, 5th: NOK 12.000)
Lunch and coffee:  Included in the registration fee

Notes:
It is possible to register for day 1 only - if advanced testbenches are not of interest;
- or days 2-3 only - if you already have extensive working knowledge of UVVM Utility Library and methodology - including related BFMs.
Send request to info@bitvis.no

Course responsible: Espen Tallaksen, Bitvis AS     (Mobile: +47 934 21 277)
Registration: On email to info@bitvis.no
Please give the following info: Full name, Company, email, mobile phone, invoice address and any potential invoice reference if needed.
Deadline for registration:  The course will be held independent of number of participants as we already have sufficient interest.
Seating is limited, and priority will be given based on time of registration.

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Efficiency and quality is all a question of overview, readability, maintainability and re-use, - and a good architecture is the answer.

A description of the course and related info can be found *** HERE ***