Accelerating FPGA VHDL Verification, Stockholm, April 20-21

Published: 20. Apr 2016

Accelerating FPGA VHDL Verification
- Including UVVM Utility Library and VVC Framework

Date:           April 20-21, 2016

Time of day:  Wednesday 9:00-17:00, Thursday 9:00-16:00

Language:     English

Place:           Stockholm, Sveavägen 64 (Realtime Embedded's office)

Registration fee: SEK 10.900  (+VAT)  
      for multiple participants from the same company:
      2nd: SEK 10.000, 3rd: SEK 9.000, 4th: SEK 8.000, 5th: SEK 7.000)    

Lunch and coffee:  Included in the registration fee

Course responsible: Espen Tallaksen, Bitvis AS     (Mobile: +47 934 21 277)

Registration: By email to Espen.Tallaksen@bitvis.no or to Realtime Embedded AB 

The course will be held in cooperation with Realtime Embedded (Stockholm) (for adminstrative issues in Sweden). 

Efficiency and quality is all a question of overview, readability, maintainability and re-use, - and UVVM is the answer.

A description of the course and related info can be found *HERE*

Please note that the previous course 'FPGA Development Best Practices' is now split into two different courses:
Accelerating FPGA Design (Digital Design; language, tool and technology independent )
- Accelerating FPGA VHDL Verification (Structured verification with examples from UVVM)