Welcome to Bitvis

Bitvis Utility Library v2.2.1 is released
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Guest lectures at UiO and NTNU
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FPGA-forum: Final programme available
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FPGA VHDL Workshop at FPGA-forum
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Guest lectures in Bergen and Oslo
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Matlab Expo 2014 - Nordic
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Advanced VHDL Testbenches and Verification (5 days)
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FPGA-forum 2014
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FPGAs: Establishing a 'Fit for Purpose' Design Flow
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the leading independent design centre in Norway for

Embedded Software & FPGA/ASIC 

with respect to

  • Quality and Risk - in the project and the product
  • Efficiency and Total project development progress
  • Customer hand-over

due to our strong focus on

  • Design Architecture and Layering - at all levels
  • Verification and Test - and a good structure for such
  • Knowledge of pitfalls and active risk prevention
  • Implementation proposals, Walkthrough and Good reviews
  • Automation when feasible

with the help of

  • A coordinated development methodology
  • The shared knowledge from our Best Practices course
  • Our tools for embedded system design
  • Our verification libraries

We also share our knowledge on numerous seminars, a Best Practices course, an open source verification library, - and guest lectures at the main universities for embedded systems design in Norway (University of Oslo, University of Bergen and Norwegian University of Science and Technology in Trondheim).